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| MC10EP16T, MC100EP16T 3.3V / 5V ECL Differential Receiver/Driver with Internal Termination The EP16T is a world-class differential receiver/driver. The device is functionally equivalent to the EP16 with internal termination resistors. A 50 W resistor is connected from the D input to the VT pin and from the D input to the VT pin. Tie the VT and VT pins to VTT supply (VCC - 2 V) for parallel termination or connect VT and VT pins for 100 W input series termination. Special considerations are required for differential inputs under No Signal conditions to prevent instability. The 100 Series contains temperature compensation. http://onsemi.com MARKING DIAGRAMS* 8 8 1 SO-8 D SUFFIX CASE 751 HEP61 ALYW 1 1 8 KEP61 ALYW * 220 ps Typical Propagation Delay * Maximum Frequency > 3 GHz Typical * PECL Mode Operating Range: VCC = 3.0 V to 5.5 V * * with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V Internal 50 W Termination Resistors 8 1 TSSOP-8 DT SUFFIX CASE 948R 8 HP61 ALYW 1 8 KP61 ALYW 1 H = MC10 K = MC100 A = Assembly Location L = Wafer Lot Y = Year W = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Device MC10EP16TD MC10EP16TDR2 MC100EP16TD MC100EP16TDR2 MC10EP16TDT MC10EP16TDTR2 MC100EP16TDT Package SO-8 SO-8 SO-8 SO-8 TSSOP-8 TSSOP-8 TSSOP-8 Shipping 98 Units/Rail 2500 Tape & Reel 98 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel 100 Units/Rail 2500 Tape & Reel MC100EP16TDTR2 TSSOP-8 (c) Semiconductor Components Industries, LLC, 2002 1 September, 2002 - Rev. 3 Publication Order Number: MC10EP16T/D MC10EP16T, MC100EP16T VT 1 50 W 8 VCC PIN DESCRIPTION 7 Q PIN D, D Q, Q VCC VEE VT VT FUNCTION ECL Data Inputs ECL Data Outputs Positive Supply Negative Supply 50 W Termination Resistor to D 50 W Termination Resistor to D D 2 D 3 50 W 6 Q VT 4 5 VEE Figure 1. 8-Lead Pinout (Top View) and Logic Diagram ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Human Body Model Machine Model Charged Device Model Value N/A N/A > 4 kV > 200 V > 2 kV Level 1 UL-94 V-0 @ 0.125 in 167 Moisture Sensitivity, Indefinite Time Out of Drypack (Note 1) Flammability Rating Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 1. For additional information, see Application Note AND8003/D. Oxygen Index: 28 to 34 MAXIMUM RATINGS (Note 2) Symbol VCC VEE VI Iout IBB TA Tstg JA JC JA JC Tsol Parameter PECL Mode Power Supply NECL Mode Power Supply PECL Mode In ut Voltage Input NECL Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 LFPM 500 LFPM std bd 0 LFPM 500 LFPM std bd <2 to 3 sec @ 248C 8 SOIC 8 SOIC 8 SOIC 8 TSSOP 8 TSSOP 8 TSSOP Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 190 130 41 to 44 185 140 41 to 44 265 Units V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C 2. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 MC10EP16T, MC100EP16T 10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3) -40C Symbol IEE VOH VOL VIH VIL VIHCMR RT IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 4) Output LOW Voltage (Note 4) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 5) Internal Termination Resistor Input HIGH Current Input LOW Current -150 Min 16 2165 1365 2090 1365 2.0 43 Typ 23 2290 1490 Max 31 2415 1615 2415 1690 3.3 57 150 -150 Min 16 2230 1430 2155 1430 2.0 43 50 25C Typ 23 2355 1555 Max 31 2480 1680 2480 1755 3.3 57 150 -150 Min 16 2290 1490 2215 1490 2.0 43 85C Typ 23 2415 1615 Max 31 2540 1740 2540 1815 3.3 57 150 Unit mA mV mV mV mV V W A A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 4. All loading with 50 W to VCC-2.0 volts. 5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6) -40C Symbol IEE VOH VOL VIH VIL VIHCMR RT IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 7) Output LOW Voltage (Note 7) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 8) Internal Termination Resistor Input HIGH Current Input LOW Current -150 Min 16 3865 3065 3790 3065 2.0 43 Typ 23 3990 3190 Max 31 4115 3315 4115 3390 5.0 57 150 -150 Min 16 3930 3130 3855 3130 2.0 43 50 25C Typ 23 4055 3255 Max 31 4180 3380 4180 3455 5.0 57 150 -150 Min 16 3990 3190 3915 3190 2.0 43 85C Typ 23 4115 3315 Max 31 4240 3440 4240 3515 5.0 57 150 Unit mA mV mV mV mV V W A A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 7. All loading with 50 W to VCC-2.0 volts. 8. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 10EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 9) -40C Symbol IEE VOH VOL VIH VIL VIHCMR RT IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 10) Output LOW Voltage (Note 10) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 11) Internal Termination Resistor Input HIGH Current Input LOW Current -150 Min 16 -1135 -1935 -1210 -1935 VEE+2.0 43 Typ 23 -1010 -1810 Max 31 -885 -1685 -885 -1610 0.0 57 150 -150 Min 16 -1070 -1870 -1145 -1870 VEE+2.0 43 50 25C Typ 23 -945 -1745 Max 31 -820 -1620 -820 -1545 0.0 57 150 -150 Min 16 -1010 -1810 -1085 -1810 VEE+2.0 43 85C Typ 23 -885 -1685 Max 31 -760 -1560 -760 -1485 0.0 57 150 Unit mA mV mV mV mV V W A A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 9. Input and output parameters vary 1:1 with VCC. 10. All loading with 50 W to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 3 MC10EP16T, MC100EP16T 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 12) -40C Symbol IEE VOH VOL VIH VIL VIHCMR RT IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 13) Output LOW Voltage (Note 13) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 14) Internal Termination Resistor Input HIGH Current Input LOW Current -150 Min 18 2155 1355 2075 1355 2.0 43 Typ 25 2280 1480 Max 35 2405 1605 2420 1675 3.3 57 150 -150 Min 20 2155 1355 2075 1355 2.0 43 50 25C Typ 27 2280 1480 Max 37 2405 1605 2420 1675 3.3 57 150 -150 Min 22 2155 1355 2075 1355 2.0 43 85C Typ 29 2280 1480 Max 39 2405 1605 2420 1675 3.3 57 150 Unit mA mV mV mV mV V W A A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 12. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -2.2 V. 13. All loading with 50 W to VCC-2.0 volts. 14. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 15) -40C Symbol IEE VOH VOL VIH VIL VIHCMR RT IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 16) Output LOW Voltage (Note 16) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 17) Internal Termination Resistor Input HIGH Current Input LOW Current -150 Min 18 3855 3055 3775 3055 2.0 43 Typ 25 3980 3180 Max 35 4105 3305 4120 3375 5.0 57 150 -150 Min 20 3855 3055 3775 3055 2.0 43 50 25C Typ 27 3980 3180 Max 37 4105 3305 4120 3375 5.0 57 150 -150 Min 22 3855 3055 3775 3055 2.0 43 85C Typ 29 3980 3180 Max 39 4105 3305 4120 3375 5.0 57 150 Unit mA mV mV mV mV V W A A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 15. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to -0.5 V. 16. All loading with 50 W to VCC-2.0 volts. 17. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. 100EP DC CHARACTERISTICS, NECL VCC = 0 V; VEE = -5.5 V to -3.0 V (Note 18) -40C Symbol IEE VOH VOL VIH VIL VIHCMR RT IIH IIL Characteristic Power Supply Current Output HIGH Voltage (Note 19) Output LOW Voltage (Note 19) Input HIGH Voltage (Single-Ended) Input LOW Voltage (Single-Ended) Input HIGH Voltage Common Mode Range (Differential) (Note 20) Internal Termination Resistor Input HIGH Current Input LOW Current -150 Min 18 -1145 -1945 -1225 -1945 VEE+2.0 43 Typ 25 -1020 -1820 Max 35 -895 -1695 -880 -1625 0.0 57 150 -150 Min 20 -1145 -1945 -1225 -1945 VEE+2.0 43 50 25C Typ 27 -1020 -1820 Max 37 -895 -1695 -880 -1625 0.0 57 150 -150 Min 22 -1145 -1945 -1225 -1945 VEE+2.0 43 85C Typ 29 -1020 -1820 Max 39 -895 -1695 -880 -1625 0.0 57 150 Unit mA mV mV mV mV V W A A NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained. 18. Input and output parameters vary 1:1 with VCC. 19. All loading with 50 W to VCC-2.0 volts. 20. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal. http://onsemi.com 4 MC10EP16T, MC100EP16T AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -5.5 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 21) -40C Symbol fmax tPLH, tPHL tSKEW tJITTER VPP tr tf Characteristic Maximum Frequency (See Figure 2 Fmax/JITTER) Propagation Delay to Output Differential Duty Cycle Skew (Note 22) Cycle-to-Cycle Jitter (See Figure 2 Fmax/JITTER) Input Voltage Swing (Differential) Output Rise/Fall Times (20% - 80%) Q, Q 150 70 150 Min Typ >3 230 5.0 0.2 800 120 300 20 <1 1200 170 150 80 150 Max Min 25C Typ >3 240 5.0 0.2 800 130 300 20 <1 1200 180 150 100 200 Max Min 85C Typ >3 275 5.0 0.2 800 140 350 20 <1 1200 200 Max Unit GHz ps ps ps mV ps 21. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC-2.0 V. 22. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs. 900 800 VOUTpp (mV) 700 600 500 400 300 200 100 0 9 JITTEROUT ps (RMS) 8 7 6 5 4 3 2 1 EEEEEEEEEEEEEEEE EEEEEEEEEEEEEEEE EE EEEEEEEEEEEEEEEE EE (JITTER) 0 500 1000 1500 2000 2500 3000 3500 4000 FREQUENCY (MHz) Figure 2. Fmax/Jitter http://onsemi.com 5 MC10EP16T, MC100EP16T Q Driver Device Q 50 W 50 W D Receiver Device D V TT V TT = V CC - 2.0 V Figure 3. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 - Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 AN1405 AN1406 AN1504 AN1568 AN1650 AN1672 AND8001 AND8002 AND8009 AND8020 - - - - - - - - - - - ECLinPS Circuit Performance at Non-Standard VIH Levels ECL Clock Distribution Techniques Designing with PECL (ECL at +5.0 V) Metastability and the ECLinPS Family Interfacing Between LVDS and ECL Using Wire-OR Ties in ECLinPS Designs The ECL Translator Guide Odd Number Counters Design Marking and Date Codes ECLinPS Plus Spice I/O Model Kit Termination of ECL Logic Devices For an updated list of Application Notes, please see our website at http://onsemi.com. http://onsemi.com 6 MC10EP16T, MC100EP16T PACKAGE DIMENSIONS SO-8 D SUFFIX PLASTIC SOIC PACKAGE CASE 751-07 ISSUE AA -X- A 8 5 B 1 4 S 0.25 (0.010) M Y M -Y- G C -Z- H D 0.25 (0.010) M SEATING PLANE K NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDAARD IS 751-07 MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244 N X 45 _ 0.10 (0.004) M J ZY S X S DIM A B C D G H J K M N S TSSOP-8 DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948R-02 ISSUE A 8x K REF 0.10 (0.004) M 0.15 (0.006) T U S 2X TU S V S L/2 8 5 L 1 PIN 1 IDENT 4 B -U- 0.25 (0.010) M 0.15 (0.006) T U S A -V- F DETAIL E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 6. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 2.90 3.10 2.90 3.10 0.80 1.10 0.05 0.15 0.40 0.70 0.65 BSC 0.25 0.40 4.90 BSC 0_ 6_ INCHES MIN MAX 0.114 0.122 0.114 0.122 0.031 0.043 0.002 0.006 0.016 0.028 0.026 BSC 0.010 0.016 0.193 BSC 0_ 6_ C 0.10 (0.004) -T- SEATING PLANE D -W- G DETAIL E DIM A B C D F G K L M http://onsemi.com 7 MC10EP16T, MC100EP16T ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative. http://onsemi.com 8 MC10EP16T/D |
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